1. Field of the Invention
The present invention relates to a semiconductor device and a test system therefor, and particularly to a test circuit for the input/output (I/O) interface of a semiconductor device.
2. Description of the Prior Art
A semiconductor test device (hereinafter referred to as an LSI tester) is used to verify the operation of a semiconductor device (LSI). To perform the test at the same speed as the system operation speed, the LSI tester must have an operation speed as high as that of the I/O interface of the LSI.
Brief description will be made below of a conventional LSI test. FIG. 6 is a block diagram showing a conventional test system for a semiconductor device. In the figure, reference numeral 1001 denotes an LSI tester; 1002 denotes a DUT board; 1003 denotes an LSI; 1004 denotes a pin card; and 1005 denotes circuit elements such as comparators and drivers. By use of computer control, the LSI tester 1001 creates an environment similar to the actual operation environment in which the LSI 1003 is operated, and determines whether or not the LSI 1003 is defective. The LSI tester 1001 includes a timing generator, a test-pattern generator, a formatter, and a power source, and applies an input signal to the LSI 1003 and compares the output response with its prepared expected value. The pin card 1004 is the final output stage producing a predetermined waveform, and includes circuit elements such as comparators to compare data output from the LSI 1003 with its expected value.
To perform a functional test on the LSI 1003, test vectors generated by the LSI tester are applied to the LSI 1003, and the output responses are compared with their expected values in order to verify the operation of the core logic including that of the input/output section.
Having a circuit configuration as described above, the conventional test system for semiconductor devices is not economical when applied to mass production of, particularly, multipin LSIs having a Gbps-class I/O since the high-speed LSI tester for those LSIs is expensive.
The high speed operation of the 1-Gbps-class LSI and an I/O timing (Setup, Hold, CLK_to_Q) of several tens to several hundreds of ps are already an operation limit and a timing limit of the conventional test system for semiconductor devices, making it difficult to perform a highly reliable test.
One method for solving the above problem is to externally connect between the output terminals and the input terminals of an LSI (or LSIs) so as to perform an operation test on the I/O interface at the actual operation speed (using a loop or connecting one chip with another). In this connection, Japanese Patent Application No. 2000-95552 (application number) discloses a semiconductor device having a test pattern generator and a data compressor therein.
On the other hand, JP-A No. 3-117214 (1991) discloses an example in which the input pins and the output pins of a single LSI or a plurality of LSIs are connected in a loop, and an actual communication operation test is performed on the I/O interface of the LSI (or LSIs). However, the output section of the above system does not include a test data generator for testing the LSI at the actual operation speed. Furthermore, its input section does not include: a comparator for sequentially comparing external data with its expected-value data supplied from the test data generator; a delay circuit for adjusting the comparison timing; and a strobe function.